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publication number S72WS-P_00 revision a amendment 4 issue date may 29, 2006 S72WS-P based mcp/pop products S72WS-P based mcp/pop products cover sheet 1.8 volt-only x16 flash memory and sdram on split bus simultaneous read/write , burst mode nor flash nand flash or nand interface ornand ? flash on bus 1 mobile sdram on bus 2 data sheet (advance information) notice to readers: this document states the current technical specifications regarding the spansion product(s) described herein. each product described herein may be designated as advance information, preliminary, or full production. see notice on data sheet designations for definitions.
ii S72WS-P based mcp/pop products S72WS-P_00_a4 may 29, 2006 data sheet (advance information) notice on data sheet designations spansion llc issues data sheets with advance information or preliminary designations to advise readers of product information or intended specifications throughout the product life cycle, including development, qualification, initial production, and full production. in all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. the following descriptions of spansion data sheet designations are presented here to highlight their presence and definitions. advance information the advance information designation indicates that spansion llc is developing one or more specific products, but has not committed any design to production. information presented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. spansion llc therefore places the following conditions upon advance information content: ?this document contains information on one or more products under development at spansion llc. the information is intended to help you evaluate this product. do not design in this product without contacting the factory. spansion llc reserves the right to change or discontinue work on this proposed product without notice.? preliminary the preliminary designation indicates that the product development has progressed such that a commitment to production has taken place. this designation covers several aspects of the product life cycle, including product qualification, initial production, and the subsequent phases in the manufacturing process that occur before full production is achieved. changes to the technical specifications presented in a preliminary document should be expected while keeping these aspects of production under consideration. spansion places the following conditions upon preliminary content: ?this document states the current technical specifications regarding the spansion product(s) described herein. the preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications.? combination some data sheets contain a combination of products with different designations (advance information, preliminary, or full production). this type of document distinguishes these products and their designations wherever necessary, typically on the first page, the ordering information page, and pages with the dc characteristics table and the ac erase and program table (in the table notes). the disclaimer on the first page refers the reader to the notice on this page. full production (no designation on document) when a product has been in production for a period of time such that no changes or only nominal changes are expected, the preliminary designation is removed from the data sheet. nominal changes may include those affecting the number of ordering part numbers available, such as the addition or deletion of a speed option, temperature range, package type, or v io range. changes may also include those needed to clarify a description or to correct a typographical error or incorrect specification. spansion llc applies the following conditions to documents in this category: ?this document states the current technical specifications regarding the spansion product(s) described herein. spansion llc deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. however, typographical or specification corrections, or modifications to the valid combinations offered may occur.? questions regarding these document designations may be directed to your local amd or fujitsu sales office.
this document contains information on one or more products under development at spans ion llc. the information is intended to he lp you evaluate this product. do not design in this product without contacting the fact ory. spansion llc reserves the right to change or discontinue work on this proposed product without notice. publication number S72WS-P_00 revision a amendment 4 issue date may 29, 2006 features ? power supply voltage of 1.7 to 1.95v ? flash access time: 80 ns for nor flash, 25 ns for ornand flash ? flash burst frequencies: 66 mhz, 80 mhz, 108 mhz ? mobile sdram burst frequency: 104 mhz (sdr), 133 mhz (ddr) ? package: ? 9.0 x 12.0 mm mcp ? 11.0 x 13.0 mm mcp ? 15.0 x 15.0 mm package-on-package (pop) ? operating temperature ? ?25c to +85c (wireless) the s72ws series is a product line of stacked packages and consists of: ? one or two nor flash memory die ? one nand interface ornand die ? separate bus for one or more mobile sdram die the products covered by this document are listed in the table below. note: for a full list of opns, please contact the local sales representative or refer to the ordering information valid combinations tables. for detailed specifications, please refer to the individual data sheets. S72WS-P based mcp/pop products 1.8 volt-only x16 flash memory and sdram on split bus simultaneous read/write , burst mode nor flash nand flash or nand interface ornand ? flash on bus 1 mobile sdram on bus 2 data sheet (advance information) device nor flash density ornand ? flash density nand flash density dram density 512mb 256mb 128mb 1024mb 512mb 512mb 512mb 256mb 128mb s72ws256pd0 (mcp) x x (ddr) s72ws256pd0 (pop) x x (ddr) s72ws512pe0 (mcp) x x (sdr) s72ws512pef (pop) x x x (sdr) s72ws512pef (pop) x x x (sdr) s72ws512pff (mcp) x x x (ddr) s72ws512pff (pop) x x x (ddr) s72ws512pff (mcp) x x x (ddr) s72ws512pff (pop) x x x (ddr) s72ws512pfg (mcp) x x x (ddr) s72ws512pfg (pop) x x x (ddr) document publication identification number (pid) s29ws-p s29ws-p_00 s30ms-p s30ms-p_00 128 mb mobile ddr-dram type 5 sdram_07 256 mb mobile sdr-dram type 2 sdram_05 512 mb mobile ddr-dram type 1 sdram_09 512 mb mobile sdr-dram type 4 sdram_06 512 mb nand type 1 nand_01 512 mb mobile ddr-dram type 5 dram_04
2 S72WS-P based mcp/pop products S72WS-P_00_a4 may 29, 2006 data sheet (advance information) 1. product selector guide 1.1 nor flash + dram products 1.2 nor flash + ornand flash + dram products 1.3 nor flash + nand flash + dram products device nor flash density nor flash speed dram density dram speed dram supplier package s72ws256pd0kfklg 256 mb 66 mhz 128 mb 133 mhz (ddr) type 5 pop 15 x 15 mm s72ws256pd0hf6lg mcp 9 x 12 mm s72ws512pe0hf61r 512 mb 80 mhz 256 mb 104 mhz (sdr) type 2 mcp 9 x 12 mm device-model# nor flash density nor flash speed ornand flash density ornand bus width ecc required dram density dram speed dram supplier package s72ws512pefkfkhh 512 mb 66 mhz 512mb x16 yes 256 mb 133 mhz (ddr) ty p e 2 pop 15 x 15 mm 160-ball s72ws512pffkfkgh 512 mb ty p e 1 pop 15 x 15 mm 160-ball s72ws512pffjf9gh mcp 11 x 13 mm 137-ball s72ws512pfgjf9gh 1024 mb mcp 11 x 13 mm 137-ball s72ws512pfgkfkgh pop 15 x 15 mm 160-ball s72ws512pffjf9ld 80 mhz 512 mb x16 yes type 5 mcp 11 x 13 mm 137-ball s72ws512pffkfkld pop 15 x 15 mm 160-ball device-model# nor flash density nor flash speed nand flash density nand bus width ecc required dram density dram speed dram supplier package s72ws512pefkfkhj 512mb 66 mhz 512mb x16 yes 256 mb 133 mhz (ddr) ty p e 2 pop 15 x 15 mm 160-ball s72ws512pffkfkgj 512 mb ty p e 1 pop 15 x 15 mm 160-ball s72ws512pffjf9gj mcp 11 x 13 mm 137- ball s72ws512pffkfkle 80 mhz type 5 pop 15 x 15 mm 160-ball s72ws512pffjf9le mcp 11 x 13 mm 137-ball
S72WS-P_00_a4 may 29, 2006 S72WS-P based mcp/pop products 3 data sheet (advance information) 2. mcp block diagram 2.1 nor flash + dram products a0-amax a0-amax f-rdy rdy f-dq15 - f-dq0 f-clk clk f-adv# adv# f-ce# ce# f-oe# oe# f-rst# reset# vss f-vss f-acc acc vssq f-vss q f-wp# wp# f-we# we# vcc f-vcc vccq f-vcc q d-ras# ras# clk d-clk d-cas# cas# clk# d-clk# d-ba0 ba0 dqs0 d-d qs0 d-ba1 ba1 dqs1 d-d qs1 d-cke cke ldqm d-dm0 d-we# we# udqm d-dm1 a0-amax dq15-dq0 d-dq15 - d-dq0 d-vcc vcc vss d-vss d-vccq vccq vssq d-vssq d-a0 - d-amax dq0-dq15 ws-p nor flash memory ddr dram memory d-ce# ce#
4 S72WS-P based mcp/pop products S72WS-P_00_a4 may 29, 2006 data sheet (advance information) 2.2 nor flash + (or)nand flash + dram products note 1. for mcps, v ss is shared between all flash (nor and ornand). also, v ssq is tied to v ss internally within the mcp. a0-a24 a0-a24 f-rdy rdy dq0-dq15 f-clk clk f-avd# avd# f-ce# ce# f-oe# oe# f-rst# reset# vss f-vss f-acc acc vssq f-vssq f-wp# wp# f-we# we# vcc f-vcc vccq f-vccq i/o0-i/o15 rb# n-cle cle n-ce# ce# n-ale ale n-pre pre vss n-vss n-re# re# n-wp# wp# n-we# we# vcc n-vcc d-ras# ras# clk d-clk d-cas# cas# clk# d-clk# d-ba0 ba0 dqs0 d-d qs0 d-ba1 ba1 dqs1 d-d qs1 d-cke cke ldqm d-dm0 d-we# we# udqm d-dm1 a0-a12 dq15-dq0 d-dq15 - d-dq0 d-vcc vcc vss d-vss d-vccq vccq vssq d-vssq d-a0 - d-a12 dq0-dq15 ws512p nor flash memory ms512p x16 ornand flash memory ddr dram memory n-ry/by# 512mb d-ce# ce#
S72WS-P_00_a4 may 29, 2006 S72WS-P based mcp/pop products 5 data sheet (advance information) 3. connection diagrams 3.1 256mb nor flash with 128mb sdr/ddr-dram note: ddr-only signals are rfus in the case of the sdr dram-based solutions. a1 a10 b4 b7 b8 b9 b3 b2 b6 a2 a3 a4 a5 a6 a7 a8 a9 b5 b1 b10 c4 c7 c8 c9 c3 c2 c6 c5 c1 c10 d4 d7 d8 d9 d3 d2 d6 d5 d1 d10 e4 e7 e8 e9 e3 e2 e6 e5 e1 e10 f4 f7 f8 f9 f3 f2 f6 f5 f1 f10 g4 g7 g8 g9 g3 g2 g6 g1 g10 h4 h7 h8 h9 h3 h2 h1 h10 j4 j7 j8 j9 j3 j2 j6 j5 j1 j10 k4 k7 k8 k9 k3 k2 k6 k5 k1 k10 l4 l7 l8 l9 l3 l2 l6 l5 l1 l10 m4 m7 m8 m9 m3 m2 m6 m5 m1 m10 n4 n7 n8 n9 n3 n2 n6 n5 n1 n10 p4 p7 p8 p9 p3 p2 p6 p5 p1 p10 d-cke d-clk d-clk# rfu d-vss d-vcc rfu d-a11 d-vss d-ce# d-ras# d-we# d-a9 d-a8 d-vssq d-vccq d-a7 d-a6 rfu d-cas# d-a10 avd# vss clk rfu rfu d-a0 f-wp# a7 d-dm0 f-acc we# a8 a11 rfu d-a5 d-vccq a3 a6 d-dm1 f-rst# rfu a19 a12 a15 d-vccq d-vssq a2 a5 a18 f-rdy a20 a9 a13 a21 d-vssq d-dq0 a1 a4 a17 a23 a10 a14 a22 d-dq15 d-dq1 a0 vss dq1 dq6 rfu a16 d-dq14 d-dq2 f1-ce# oe# dq9 dq3 dq4 dq13 dq15 rfu d-dq13 d-dq3 rfu dq0 dq10 f-vcc rfu dq12 dq7 vss d-dq12 d-dq4 rfu dq8 dq2 dq11 rfu dq5 dq14 rfu d-dq11 d-dq5 rfu rfu vss f-vcc rfu rfu f-vccq rfu d-dq10 rfu d-ba0 d-dq6 d-dq7 d-vssq d-vccq d-dq8 d-dq9 d-ba1 rfu d-dqs0 d-vss d-a1 d-a2 d-vss d-vcc d-a3 d-a4 rfu d-dqs1 dram only legend reserved for future use nor flash only ddr dram only rfu rfu rfu rfu 137-ball fine-pitch ball grid array (top view, balls facing down)
6 S72WS-P based mcp/pop products S72WS-P_00_a4 may 29, 2006 data sheet (advance information) 3.2 512mb nor flash with 512-mb (or)nan d on bus 1 and 512-mb dram on bus 2 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 b1 b2 b3 b4 b5 b6 b7 b8 b10 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 e1 e2 e3 e4 e5 e6 e7 e8 e9 e10 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 g1 g2 g3 g4 g6 g7 g8 g9 g10 h1 h2 h3 h4 h7 h8 h9 h10 j1 j2 j3 j4 j5 j6 j7 j8 j9 j10 k1 k2 k3 k4 k5 k6 k7 k8 k9 k10 l1 l2 l3 l4 l5 l6 l7 l8 l9 l10 m1 m2 m3 m4 m5 m6 m7 m8 m9 m10 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 d-cke d-clk rfu d-v ss d-v cc d-a12 d-a11 d-v ss d-ce# d-ras# d-we# d-a9 d-a8 d-v ssq d-v ccq d-a7 d-a6 rfu d-cas# d-a10 f-avd# v ss f-clk rfu f-v cc n-pre n-ale n-cle rfu d-a0 f-wp# a7 d-dm0 f-acc f-we# a8 a11 n-ce# d-a5 d-v ccq a3 a6 d-dm1 f-rst# dnu a19 a12 a15 d-v ccq d-v ssq a2 a5 a18 f-rdy a20 a9 a13 a21 d-v ssq d-dq15 a22 a14 a10 a23 a17 a4 a1 d-dq0 d-dq1 a0 vss dq1 dq6 a24 a16 d-dq14 d-dq13 dnu dq15 dq13 dq4 dq3 dq9 f-oe# f1-ce# d-dq2 d-dq3 dnu dq0 dq10 f-v cc n-v cc dq12 dq7 v ss d-dq12 d-dq11 n-wp# dq14 dq5 rfu dq11 dq2 dq8 n-vcc d-dq4 d-dq5 rfu rfu v ss f-v cc rfu dnu f-v ccq dnu d-dq10 n-re# d-ba1 d-dq9 d-dq8 d-v ccq d-v ssq d-dq7 d-dq6 d-ba0 n-we# d-dqs0 d-v ss d-a1 d-a2 d-v ss d-v cc d-a3 d-a4 n-ry/by# legend do not use nor flash only ornand flash only reserved for future use dram only all flash shared d-clk# d-dqs1 b9 p9 137-ball fine-pitch ball grid array (top view, balls facing down)
S72WS-P_00_a4 may 29, 2006 S72WS-P based mcp/pop products 7 data sheet (advance information) 3.2.0.1 special handling inst ructions for fbga package special handling is required for flash memory products in fbga packages. flash memory devices in fbga packages may be damaged if exposed to ultrasonic cleaning methods. the package and/or data integrity may be compromised if the package body is exposed to temperatures above 150c for prolonged periods of time. 3.2.1 package-on-package connection diagram 3.2.2 look-ahead ballout for future designs please refer to the design-in scalable wireless solutions with spansion products application note (publication number: design_scalable_wireless_a0_e). contact your local spansion sales representative for more details. 34 5 6 7 8 9 10 11 12 13 14 1 5 16 17 18 19 c d e f g h j k l m n p r t u v w y 20 no connect ornand flash only flash share d only legen d f-rst# 21 22 f1-ce# n1- c e# rfu n-re# n-wp# f-we# f-wp# f-oe# f-acc 12 n-we# n-ry/ b y# d-dq14 f-adv# f-wait rfu f-clk rfu n c n c n-cle rfu n-ale f-a24 n c nc d-v dd a b aa ab nor flash only reserve d for future use ddr dram only rfu rfu rfu rfu rfu rfu rfu rfu rfu rfu d-dq1 5 d-dq13 d-dq12 d-dq11 d-dq10 d-dq9 d-dq8 d-dq7 d-dq6 d-dq 5 d-dq4 d-dq3 d-dq2 d-dq1 d-dq0 f-a1 f-a2 f-a0 f-a3 f-a4 f-a 5 f-a6 f-a7 f-a8 f-a9 f-a10 f-a11 f-a12 f-a13 f-a14 f-a1 5 f-a16 f-a17 f-a18 f-a19 f-a20 f-a21 f-a22 f-a23 f-dq14/ n-adq14 f-dq1 5 / n-adq1 5 f-dq12/ n-adq12 f-dq13/ n-adq13 f-dq10/ n-adq10 f-dq11/ n-adq11 f-dq8/ n-adq8 f-dq9/ n-adq9 f-dq6/ n-adq6 f-dq7/ n-adq7 f-dq4/ n-adq4 f-dq 5 / n-adq 5 f-dq2/ n-adq2 f-dq3/ n-adq3 f-dq0/ n-adq0 f-dq1/ n-adq1 d-a0 d-a1 d-a2 d-a3 d-a4 d-a 5 d-a6 d-a7 d-a8 d-a9 d-a10 d-a11 d-a12 d-v ss d-v ss f-v ss f-v ssq f-v ssq n-v ss f-v ssq d-v ss d-v ss n-v ss f-v ssq f-v ssq f-v ssq n-pre f-v ssq f-v ss d-v ssq d-v ss d-v ssq d-v ssq d-v ssq f-v cc f-v ccq f-v ccq f-v ccq n-v cc d-v dd d-v dd f-v ccq f-v ccq f-v ccq n-v cc f-v cc f-v ccq f-v ccq d-v dd d-v ddq d-v dd d-v ddq d-v ddq d-v ddq d-we# d-ba0 d-ba1 d1-cs# d-ras# d-cas# d-cke d-clk d-clk# d-dm1 d-dqs1 d-dm0 d-dqs0 f2-ce# 160-ball fine pitch ball grid array (top view, balls facing down)
8 S72WS-P based mcp/pop products S72WS-P_00_a4 may 29, 2006 data sheet (advance information) 3.3 nor flash and dram input/output descriptions 3.3.1 ornand signal descriptions amax-a0 = nor flash address inputs dq15-dq0 = flash data input/output, shared between nor and ornand flash. dq0-dq7 shared for x8 ornand f-ce# = nor flash chip-enable input #1. asynchronous relative to clk for burst mode. f-oe# = nor flash output enable input. asynchronous relative to clk for burst mode. f-we# = nor flash write enable input. f-v cc = nor flash device power supply (1.7 v - 1.95v). f-v ccq = input/output buffer power supply. v ss =ground rfu = reserved for future use f-rdy = flash ready output. indicates the status of the burst read. vol = data valid. f-clk = nor flash clock. the first rising edge of clk in conjunction with avd# low latches the address input and activates burst mode operation. after the initial word is output, subsequent rising edges of clk increment the internal address counter. clk should remain low during asynchronous access. f-avd# = nor flash address valid input. indicates to device that the valid address is present on the address inputs. vil = for asynchronous mode, indicates valid address; for burst mode, causes starting address to be latched on rising edge of clk. vih= device ignores address inputs f-rst# = nor flash hardware reset input. vil= device resets and returns to reading array data f-wp# = nor flash hardware write protect input. vil = disables program and erase functions in the four outermost sectors. f-acc = nor flash accelerated input. at vhh, accelerates programming; automatically places device in unlock bypass mode. at vil, disables all program and erase functions. should be at vih for all other conditions. d-amax-d-a0 = sdram address inputs d-dq15-d-dq0 = sdram data input/output d-clk = sdram system clock d-ce# = sdram chip select d-cke = sdram clock enable d-ba1-ba0 = sdram bank select d-ras# = sdram row address strobe d-cas# = sdram column address strobe d-dm1-d-dm0 = sdram data input/output mask d-we# = sdram write enable input d-v ss = sdram ground d-clk# = ddr sdram clock - in addition to d-clk, this signal is available for ddrams that need clk# for normal operations d-v ssq = sdram input/output buffer ground d-v ccq = sdram input/output buffer power supply d-v cc = sdram device power supply d-dqs0 - d- dqs1 = ddr sdram data strobe pins. dqs provides the read data strobes (as output) and the write data strobes (as input). each dqs pin corresponds to eight dq pins, respectively. n-pre = ornand power-on read enable. tie to v ss on customer board if not used n-ale = ornand address latch enable n-cle = ornand command latch enable n-ce# = ornand chip-enable n-wp# = ornand write-protect n-we# = ornand write-enable n-re# = ornand read-enable n-ry/by# = ornand ready-busy n-i/o0-n-i/o15 = ornand i/o signals (i/o0-i/o7 for x8 bus width) n-v cc = ornand power supply
S72WS-P_00_a4 may 29, 2006 S72WS-P based mcp/pop products 9 data sheet (advance information) 4. ordering information the order number is formed by a valid combinations of the following: s72ws 512 p d0 hf 0 l g 0 packing type 0 = tray 2 = 7? tape and reel 3 = 13? tape and reel model number 2 g = 66mhz/133mhz speed, no data flash h = 66mhz/133mhz speed, spansion ms-p as data flash j = 66mhz/133mhz speed, nand type 1 as data flash r = 80mhz/104mhz speed, no data flash d = 80mhz/133mhz speed, spansion ms-p as data flash e = 80mhz/133mhz speed, nand type 1 as data flash model number 1 l = x16 ddr dram type 5 g = x16 ddr dram type 1 h = x16 ddr dram type 2 1 = x16 sdr dram type 2 package descriptor depends on character 12. for a more detailed description see table 4.1 . package type & material set hf = 1.2mm mcp fbga, pb-free kf = 1.2mm pop fbga, pb-free jf = 1.4mm mcp fbga, pb-free dram & ornand flash density d0 = 128 mb dram, no data flash ef = 256mb dram, 512mb nand flash ff = 512mb dram, 512mb nand flash e0 = 256mb dram, no data flash process technology p = 90 nm, mirrorbit tm technology code flash density 256 = 256mb 512 = 512mb product family s72ws stacked products (mcp/pop) 1.8 v nor flash and ornand flash on bus 1 with mobile dram on bus 2 table 4.1 character position descriptions (sheet 1 of 2) character 12 character 13 character 14 description package area package ball count raw ball size h, j, or g 07x9mm56 0.35 mm 17x9 mm80 2 8x11.6 mm 64 3 8x11.6 mm 84 4 9x12 mm 84 5 9x12 mm 115 6 9x12 mm 137 7 11x13 mm 84 8 11x13 mm 115 9 11x13 mm 137
10 S72WS-P based mcp/pop products S72WS-P_00_a4 may 29, 2006 data sheet (advance information) 4.1 valid combinations valid combinations list configurations planned to be supported in volume for this device. consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. notes: 1. packing type 0 is standard. specify other options as required. 2. bga package marking omits leading s and packing type designator from ordering part number. k a 11x11 mm 112 0.45 mm b 11x11 mm 112 0.50 mm d 12x12 mm 128 0.45 mm f 12x12 mm 128 0.50 mm g 14x14 mm 152 0.45 mm h 14x14 mm 152 0.50 mm j 15x15 mm 160 0.45 mm k 15x15 mm 160 0.50 mm l 17x17 mm 192 0.45 mm m 17x17 mm 192 0.50 mm table 4.1 character position descriptions (sheet 2 of 2) character 12 character 13 character 14 description package area package ball count raw ball size S72WS-P valid combinations nor flash speed dram supplier dram speed package type package markings base ordering number package & material set package descriptor packing type s72ws256pd0 kf k 0, 2, 3 (note 1) 66 mhz type 5 133 mhz 15x15 mm (pop) (note 2) hf 6 9x12 mm (mcp) s72ws512pe0 hf 6 80 mhz type 2 104 mhz 9x12 mm (mcp) s72ws512pef kf k 66 mhz type 2 133 mhz 15x15 mm (pop) s72ws512pff hf 6 66 mhz type 1 133 mhz 15x15 mm (pop) jf 9 66 mhz type 1 11x13 mm (mcp) 80 mhz type 5 kf k 66 mhz type 1 15x15 mm (pop) 80 mhz type 5 s72ws512pfg jf 9 66 mhz type 1 133 mhz 11x13 mm (mcp) kf k 15x15 mm (pop)
S72WS-P_00_a4 may 29, 2006 S72WS-P based mcp/pop products 11 data sheet (advance information) 5. physical dimensions 5.1 tld137?137-ball fine-pitch ball grid array (fbga) 12 x 9 mm package 3393\ 16-038.22a package tld 137 jedec n/a d x e 12.00 mm x 9.00 mm package symbol min nom max note a --- --- 1.20 profile a1 0.17 --- --- ball height a2 0.81 --- 0.97 body thickness d 12.00 bsc. body size e 9.00 bsc. body size d1 10.40 bsc. matrix footprint e1 7.20 bsc. matrix footprint md 14 matrix size d direction me 10 matrix size e direction n 137 ball count b 0.35 0.40 0.45 ball diameter ee 0.80 bsc. ball pitch ed 0.80 bsc ball pitch sd / se 0.40 bsc. solder ball placement g5,h5,h6 depopulated solder balls notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populted solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9. n/a 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. pn ml e1 7 se a d1 ed dc e f g h j k 10 8 9 7 6 4 3 2 1 ee 5 b pin a1 corner 7 sd bottom view c 0.08 0.20 c a e b c 0.15 (2x) c d c 0.15 (2x) index mark 10 6 b top view side view corner 137x a1 a2 a 0.15 m c 0.08 m c ab pin a1
12 S72WS-P based mcp/pop products S72WS-P_00_a4 may 29, 2006 data sheet (advance information) 5.2 fvd137?137-ball fine-pitch ball grid array (fbga) 13 x 11 mm package 3522 \ 16-038.21 \ 09.29.05 package fvd 137 jedec n/a d x e 13.00 mm x 11.00 mm note package symbol min nom max a --- --- 1.40 profile a1 0.10 --- --- ball height a2 1.09 --- 1.24 body thickness d 13.00 bsc. body size e 11.00 bsc. body size d1 10.40 bsc. matrix footprint e1 7.20 bsc. matrix footprint md 14 matrix size d direction me 10 matrix size e direction n 137 ball count ?b 0.35 0.40 0.45 ball diameter ee 0.80 bsc. ball pitch ed 0.80 bsc ball pitch sd se 0.40 bsc. solder ball placement g5,h5,h6 depopulated solder balls notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jep95, section 4.3, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populted solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. 0.08 c c 6 b 0.15 m c c ab m side view 137x 0.08 7 se e1 d1 10 9 8 6 4 5 2 1 3 ee 7 ed a corner pin a1 c d e f g h j k l m n 7 sd bottom view p c b a d e 0.15 (2x) c b c 0.15 (2x) 9 top view pin a1 corner a2 a index mark a1 0.20
S72WS-P_00_a4 may 29, 2006 S72WS-P based mcp/pop products 13 data sheet (advance information) 5.3 bwb160?160-ball fine-pitch ball grid array (fbga) 15 x 15 mm package 3 52 3 \ 16-0 38 .46 \ 02.2 3 .06 package bwb 160 jedec n/a d x e 15.00 mm x 15.00 mm note package s ymbol min nom max a --- --- 1. 3 0 profile a1 0.40 --- --- ball height a2 0.74 --- 0. 8 4 body thickne ss d 15.00 b s c. body s ize e 15.00 b s c. body s ize d1 1 3 .65 b s c. matrix footprint e1 1 3 .65 b s c. matrix footprint md 22 matrix s ize d direction me 22 matrix s ize e direction n 160 ball count n 160 maximum number of ball s r 2 number of land parameter s ? b 0.45 0.50 0.55 ball diameter ee 0.65 b s c. ball pitch ed 0.65 b s c. ball pitch s d / s e 0. 3 25 b s c. s older ball placement ? c 3 ~c20,d 3 ~d20,e 3 ~e20,f 3 ~f20 depopulated s older ball s g 3 ~g20,h 3 ~h20,j 3 ~j20,k 3 ~k20 l 3 ~l20,m 3 ~m20,n 3 ~n20,p 3 ~p20 r 3 ~r20,t 3 ~t20,u 3 ~u20,v 3 ~v20 w 3 ~w20,y 3 ~y20 note s : 1. dimen s ioning and tolerancing method s per a s me y14.5m-1 99 4. 2. all dimen s ion s are in millimeter s . 3 . ball po s ition de s ignation per jep 9 5, s ection 4. 3 , s pp-010. 4. e repre s ent s the s older ball grid pitch. 5. s ymbol "md" i s the ball matrix s ize in the "d" direction. s ymbol "me" i s the ball matrix s ize in the "e" direction. n i s the number of populted s older ball po s ition s for matrix s ize md x me. 6 dimen s ion " b " i s mea s ured at the maximum ball diameter in a plane parallel to datum c. 7 s d and s e are mea s ured with re s pect to datum s a and b and define the po s ition of the center s older ball in the outer row. when there i s an odd number of s older ball s in the outer row s d or s e = 0.000. when there i s an even number of s older ball s in the outer row, s d or s e = e/2 8 . "+" indicate s the theoretical center of depopulated ball s . 9 a1 corner to be identified by chamfer, la s er or ink mark, metallized mark indentation or other mean s . 10. outline and dimen s ion s per cu s tomer requirement. 6 b s ide view c 160x 0.15 m c a b 0.0 8 m c a b 7 d e g h s e f c corner k l n p m t u w y v r e1 j pin a1 d1 ee ed ab 1 3 4 2 5 6 7 8 7 s d 10 1 3 12 11 14 15 17 16 9 1 9 21 22 20 bottom view 1 8 aa a d e 9 corner pin a1 index mark c b 0.10 c 0.20 (2x) top view c 0.10 c 0.10 (2x) a1 a2 a
14 S72WS-P based mcp/pop products S72WS-P_00_a4 may 29, 2006 data sheet (advance information) 5.4 bta160?160-ball fine-pitch ball grid array (fbga) 15 x 15 mm package 3550 \ 16-038.55 \ 02.23.06 package bta 160 jedec n/a d x e 15.00 mm x 15.00 mm note package symbol min nom max a --- --- 1.30 profile a1 0.40 --- --- ball height a2 0.74 --- 0.84 body thickness d 15.00 bsc. body size e 15.00 bsc. body size d1 13.65 bsc. matrix footprint e1 13.65 bsc. matrix footprint md 22 matrix size d direction me 22 matrix size e direction n 160 ball count n 160 maximum number of balls r 2 number of land parameters ? b 0.45 0.50 0.55 ball diameter ee 0.65 bsc. ball pitch ed 0.65 bsc. ball pitch sd se 0.325 bsc. solder ball placement c3 ~ c20,d3 ~ d20,e3 ~ e20,f3 ~ f20 depopulated solder balls g3 ~ g20,h3 ~ h20,j3 ~ j20,k3 ~ k20 l3 ~ l20,m3 ~ m20,n3 ~ n20,p3 ~ p20 r3 ~ r20,t3 ~ t20,u3 ~ u20,v3 ~ v20 w3 ~ w20,y3 ~ y20 notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jep95, section 4.3, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populted solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. 10. outline and dimensions per customer requirement. 6 b side view c 160x 0.15 m c a b 0.08 m c a b 7 d e g h se f c corner k l n p m t u w y v r e1 j pin a1 d1 ee ed ab 1 3 4 2 5 6 7 8 7 sd 10 13 12 11 14 15 17 16 9 19 21 22 20 bottom view 18 aa a d e 9 corner pin a1 index mark c b 0.10 c 0.20 (2x) top view c 0.10 c 0.10 (2x) a1 a2 a
S72WS-P_00_a4 may 29, 2006 S72WS-P based mcp/pop products 15 data sheet (advance information) 6. revision history 6.1 revision a1 (february 23, 2006) initial release. 6.2 revision a2 (march 29, 2006) modified block diagram for section 2.1 and section 2.2 2. updated pop connection diagram in section 3.2.2 3. updated section 3.3 to append f-rdy and n-ry/by# as separate signals 6.3 revision a3 (april 11, 2006) added a note to the nor flash + (or)nand flash + dram products block diagram updated pin m8 on the 256m b nor flash with 128mb sdr/ ddr-dram connection diagram 6.4 revision a4 (may 29, 2006) added opns for products based on dram type 5 updated product selector guide updated ordering information updated valid combinations colophon the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and m anufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a s erious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in we apon system), or (2) for any use where chance of failure is intolera ble (i.e., submersible repeater and artifi cial satellite). please note that spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semic onductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection , and prevention of over-c urrent levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restriction s on export under the foreign exchange and foreign trade law of japan, the us export administration regulations or the applicable laws of any oth er country, the prior authorization by the respective government entity will be required for export of those products. trademarks and notice the contents of this document are subject to change without notice. this document may contain information on a spansion product under development by spansion. spansion reserves the right to change or discontinue work on any product without notice. the informati on in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of th ird-party rights, or any ot her warranty, express, imp lied, or statut ory. spansi on assumes no liability for any damages of any ki nd arising out of the use of t he information in this document. copyright ? 2006 spansion llc. all rights reserved. spansion, th e spansion logo, mirrorbit, ornand, hd-sim, and combinations th ereof are trademarks of spansion llc. other names are for informational purposes only and may be trademarks of their respective owner s.

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